Open Access Journal

ISSN : 2394-2320 (Online)

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

Open Access Journal

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

ISSN : 2394-2320 (Online)

Low power 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read

Author : Kalvala Srikanth 1

Date of Publication :20th November 2017

Abstract: In this paper, we are introducing a new 10T static random access memory cell having single ended decoupled read-bit line (RBL) with a 4T read port for low power operation and leakage reduction. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the VDD level for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL pre-charging level during the write and the hold mode, and are connected to true supply levels only during the read operation. The RBL is pre-charged at half the cell’s supply voltage, and is allowed to charge and discharge according to the stored data bit. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is 2.47× the size of 6T with β = 2, provides 2.3× read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and (ION/IOFF) is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved.

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