Date of Publication :24th January 2018

Abstract: Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. This paper proposes the design and implementation of 16 Bit Vedic Multiplier based on carrying save adder using the techniques of Ancient Indian Vedic Mathematics. The proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using Xilinx ISE 14.1 design suite. The design is synthesized using Artix-7 FPGA family. The Artix-7 family is based on a 28nm design which operates at 50% lower power than 45 nm technology. In this paper peak memory usage, delay, power, power-delay product and energy-delay product are the parameters taken for comparison. The results that were taken for comparison has previously done for 16 bit Vedic multiplier based on 16 bit modified carry select adder, 16 bit ripple carry adder and 16 bit kogge-stone adder[2] and here that results were constituted in this paper for comparative study with 16 bit Vedic multiplier based on carrying save adder for same parameters. This paper also gives information of Urdhva Tiryakbhyam algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed and area of multipliers. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels. So the design complexity gets reduced for inputs of larger no of bits and modularity gets increased.

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