Volume5,February 2018,

Topic : A Novel Low-Power Reversible Vedic Multiplier

Authors:P.Kiran Kumar || E.Padmaja

Abstract:In reversible computing, modelling low-power circuits is one of the most important technique. As a result of its wide range of applications, major works have been proposed in realizing reversible circuits including primary reversible gates and adders. In reversible computation, multiplier circuits play a vital role in practical applications like quantum dot cellular automata, DNA computing, nanotechnology and low-power CMOS designs. Hence superior multiplier architectures are bound to increase the efficiency of the system. The Vedic multiplier is one such optimistic solution. Implementing this with reversible logic further decreases power dissipation. In this paper, a novel reversible Vedic multiplier is proposed by making use of an algorithm or sutra called Urdhva Tiryagbhyam meaning vertical & crosswise. The power dissipation of proposed reversible multiplier design is reduced by 72.47 %. The reduction in power dissipation is highly achieved by reducing the number of gates which comprise reduction of 12.5 %. The constant inputs are reduced by 16.5 % and a reduction of 28 % is obtained in garbage outputs..

Keywords: Reversible computation, nanotechnology, DNA computing, Urdhva Tiryagbhyam, vedic multiplier

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