1. 1. J. Rose et al., “The VTR project: Architecture and CAD for FPGAs from verilog to routing,” inProc. ACM/SIGDA FPGA, 2012, pp. 77–86.
   2.  Y. Hara, H. Tomiyama, S. Honda, and H. Takada, “Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis,” J. Inf. Process., vol. 17,pp. 242–254, Oct. 2009.
   3. A. Canis et al., “LegUp: High-level synthesis for FPGA-based processor/accelerator systems,” in Proc. ACM/SIGDA FPGA, 2011, pp. 33–36.
   4. E. Ahmed and J. Rose, “The effect of LUT and cluster size on deep submicron FPGA performance and density,” IEEE Trans. Very Large Scale Integer. (VLSI), vol. 12, no. 3, pp. 288–298, Mar. 2004.
   5. J. Rose, R. Francis, D. Lewis, and P. Chow, “Architecture of field programmable gate arrays: The effect of logic block functionality on area efficiency,” IEEE J. Solid-State Circuits, vol. 25, no. 5,pp. 1217– 1225, Oct. 1990.
   6. H. Parandeh-Afshar, H. Benbihi, D. Novo, and P. Ienne, “Rethinking FPGAs: Elude the flexibility excess of LUTs with and-inverter cones,” in Proc. ACM/SIGDA FPGA, 2012, pp. 119–128.
   7. J. Anderson and Q. Wang, “Improving logic density through synthesis inspired architecture,” inProc. IEEE FPL, Aug./Sep. 2009, pp. 105–111.
   8. J. Anderson and Q. Wang, “Area-efficient FPGA logic elements: Architecture and synthesis,” inProc. ASP DAC, 2011, pp. 369–375.