Author : Pallavi Mamidala 1
Date of Publication :22nd November 2017
Abstract: Hybrid configurable logic block architectures for field-programmable gate arrays that contain a mixture of lookup tables and hardened multiplexers are evaluated toward the goal of higher logic density and area reduction. Multiple hybrid configurable logic block architectures, both nonfracturable and fracturable with varying MUX:LUT logic element ratios are evaluated across two benchmark suites (VTR and CHStone) using a custom tool flow consisting of LegUp-HLS, Odin-II front-end synthesis, ABC logic synthesis and technology mapping, and VPR for packing, placement, routing, and architecture exploration. VPR is used to model the new hybrid configurable logic block and verify post place and route implementation. In this paper experimentally, we show that for nonfracturable architectures, without any mapped optimizations, we naturally save up to∼8% area post place and route. For fracturable architectures, experiments show that only marginal gains are seen after place-and-route up to∼2%. For both nonfracturable and fracturable architectures, we see minimal impact on timing performance for the architectures with best areaefficiency.
Reference :
-
- J. Rose et al., “The VTR project: Architecture and CAD for FPGAs from verilog to routing,” inProc. ACM/SIGDA FPGA, 2012, pp. 77–86.
- Y. Hara, H. Tomiyama, S. Honda, and H. Takada, “Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis,” J. Inf. Process., vol. 17,pp. 242–254, Oct. 2009.
- A. Canis et al., “LegUp: High-level synthesis for FPGA-based processor/accelerator systems,” in Proc. ACM/SIGDA FPGA, 2011, pp. 33–36.
- E. Ahmed and J. Rose, “The effect of LUT and cluster size on deep submicron FPGA performance and density,” IEEE Trans. Very Large Scale Integer. (VLSI), vol. 12, no. 3, pp. 288–298, Mar. 2004.
- J. Rose, R. Francis, D. Lewis, and P. Chow, “Architecture of field programmable gate arrays: The effect of logic block functionality on area efficiency,” IEEE J. Solid-State Circuits, vol. 25, no. 5,pp. 1217– 1225, Oct. 1990.
- H. Parandeh-Afshar, H. Benbihi, D. Novo, and P. Ienne, “Rethinking FPGAs: Elude the flexibility excess of LUTs with and-inverter cones,” in Proc. ACM/SIGDA FPGA, 2012, pp. 119–128.
- J. Anderson and Q. Wang, “Improving logic density through synthesis inspired architecture,” inProc. IEEE FPL, Aug./Sep. 2009, pp. 105–111.
- J. Anderson and Q. Wang, “Area-efficient FPGA logic elements: Architecture and synthesis,” inProc. ASP DAC, 2011, pp. 369–375.