Author : Kalvala Srikanth 1
Date of Publication :20th November 2017
Abstract: In this paper, we are introducing a new 10T static random access memory cell having single ended decoupled read-bit line (RBL) with a 4T read port for low power operation and leakage reduction. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the VDD level for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL pre-charging level during the write and the hold mode, and are connected to true supply levels only during the read operation. The RBL is pre-charged at half the cell’s supply voltage, and is allowed to charge and discharge according to the stored data bit. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is 2.47× the size of 6T with β = 2, provides 2.3× read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and (ION/IOFF) is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved.
Reference :
-
- T. Mudge, ―Power: A first-class architectural design constraint,‖ Computer, vol. 34, no. 4, pp. 52–58, Apr. 2001. [2] N. S. Kim et al., ―Leakage current: Moore’s law meets static power,‖ Computer, vol. 36, no. 12, pp. 68–75, Dec. 2003.
- G. Venkatesh et al., ―Conservation cores: Reducing the energy of mature computations,‖ ACM SIGARCH Comput. Archit. News, vol. 38, no. 1, p. 205, 2010.
- N. Goulding-Hotta et al., ―The GreenDroid mobile application processor: An architecture for silicon’s dark future,‖ IEEE Micro, vol. 31, no. 2, pp. 86–95, Mar./Apr. 2011.
- A. Pavlov and M. Sachdev, CMOS SRAM Circuit Design and Parametric Test in NANO-Scaled Technologies: Process-Aware SRAM Design and Test, vol. 40. The Netherlands: Springer, 2008.
- J. Singh, S. P. Mohanty, and D. Pradhan, Robust SRAM Designs and Analysis. New York, NY, USA: Springer-Verlag, 2012.
- M. A. Rahma and M. Anis, Nanometer VariationTolerant SRAM: Circuits and Statistical Design for Yield. New York, NY, USA: Springer-Verlag, 2012.
- L. Chang et al., ―Stable SRAM cell design for the 32 nm node and beyond,‖ in Symp. VLSI Technol. Dig. Tech. Papers., Jun. 2005, pp. 128–129.
- M.-H. Tu et al., ―A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write