Author : Kamal Prakash Pandey 1
Date of Publication :24th January 2018
Abstract: Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. This paper proposes the design and implementation of 16 Bit Vedic Multiplier based on carrying save adder using the techniques of Ancient Indian Vedic Mathematics. The proposed Vedic multiplier is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using Xilinx ISE 14.1 design suite. The design is synthesized using Artix-7 FPGA family. The Artix-7 family is based on a 28nm design which operates at 50% lower power than 45 nm technology. In this paper peak memory usage, delay, power, power-delay product and energy-delay product are the parameters taken for comparison. The results that were taken for comparison has previously done for 16 bit Vedic multiplier based on 16 bit modified carry select adder, 16 bit ripple carry adder and 16 bit kogge-stone adder[2] and here that results were constituted in this paper for comparative study with 16 bit Vedic multiplier based on carrying save adder for same parameters. This paper also gives information of Urdhva Tiryakbhyam algorithm of Vedic Mathematics which is utilized for multiplication to improve the speed and area of multipliers. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels. So the design complexity gets reduced for inputs of larger no of bits and modularity gets increased.
Reference :
-
- Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, “Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda,” Motilal Banarasidas Publishers, pp. 5-45, Delhi, 2009
- Paras Gulati, Harsh Yadav and Manoj Kumar Taleja,” Implementation of an Efficient Multiplier Using the Vedic Multiplication Algorithm” International Conference on Computing, Communication and Automation (ICCCA), 2016
- B. Ramkumar and Harish M Kittur,” Low-Power and Area-Efficient Carry Select Adder” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 2, February 2012
- Keshab k. Parhi, “VLSI Digital Signal Processing Systems- Design and Implementation,” Wiley India Edition, 2010.
- Josmin Thomas, R.Pushpangadan, Jinesh,”Comparative Study of Performance Vedic Multiplier on The Basis of Adders Used”, IEEE International WIE Conference on Electrical and Computer Engineering, 2015
- Jasbir kaur, Lalit Sood”, Comparison between Various Types of Adder Topologies”, International Journal of Computer Science and Technology, IJCST Vol. 6, Issue 1, Jan - March 2015
- R. Uma, V. Vijayan, M. Mohanapriya, and S. Paul, “Area, delay and power comparison of adder topologies”, International Journal of VLSI design & Communication Systems (VLSICS) Vol. 3, No. 1, 2012.
- Purushottam, D. Chidgupkar and Mangesh T. Karad, “The Implementation of Vedic Algorithms in Digital Signal Processing”, UICEE, Global J. of Engg. Education, Vol.8, No.2, pp. 153-158, 2004.
- R.Sridevi, Anirudh Palakurthi, Akhila Sadhula, Hafsa Mahreen,”Design of High Speed Multiplier (Ancient Vedic Mathematics Approach”, International Journal of Engineering Research, Volume No.2, pp: 183-186, July 2013.
- Athira.T.S., Divya.R, Karthik.M, Manikandan. A,” Design of Kogge-Stone for Fast Addition”, International Journal of Industrial Electronics and Electrical Engineering, Volume-5, Issue-4, April-2017