Author : Deepak Mittal 1
Date of Publication :22nd February 2018
Abstract: Various energy recovery circuits have been proposed for reducing the power dissipation in CMOS logic circuits. This paper presents three Logic Circuits implemented using charge recovery logic. They are completely unique boost logic known as pseudo-NMOS boost logic (PNBL), to get low energy consumption and efficient-speed as compare to CMOS binary logic. PNBL is faster and compact charge recovery logic and it related to boost logic family. These logic circuits have less operating energy dissipation due to charge recovery logic. To exhibit the performance of Logic circuits are implemented with PNBL and compared with CMOS in 180nm technology. Simulation results show that logic circuits with PNBL recover the charge 57.14nJ at the frequency of 1GHZ that is approximately 105 times conserve energy as compared to conventional CMOS technology. Charge recovery logic also has one more advantage that it provided complemented and non-complemented both output at a time with small area trade-off.
Reference :
-
- Y. Zhang, L. Okamura, and T. Yoshihara,“An energy efficiency 4-bit multiplier with two-phase nonoverlap clock driven charge recovery logic,” Electronics, IEICE Transactions on, vol. E94-C, no.4, pp. 605–612, April 2011.
- J. C. Kao, W. H. Ma, V. S. Sathe, and M. Papaefthymiou, “Energy efficient low-latency 600 mhz fir with high-overdrive charge recovery logic,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP, no. 99, pp. 1–12, 2011.
- Cihun-Siyong Alex Gong, Muh-Tian Shiue, CiTong Hong, and KaliWenYao, "Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18�m CMOS," IEEE Trans. Circuits Syst. I,vol .55, No.9, pp.2595-2607, Oct. 2008.
- V. S. Sathe, J. Y. Chueh, and M. C. Papaefthymiou, “Energy-efficient ghz-class chargerecovery logic,” Solid-State Circuits, IEEE Journal of, vol. 42, no. 1, pp. 38–47, Jan. 2007.
- Changning Luo and Jianping Hu, "Single-phase adiabatic flip-flops and Sequential circuits using improved CAL circuits," IEEE ASICON'07,Guilin, China, pp. 126-129, 2007.
- D. Suvakovic and C. Salama, “Two phase nonoverlapping clock adiabatic differential cascade voltage switch logic (adcvsl),” Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International, pp.364–365, 2000.
- Y. Moon and D-K. Jeong, "An efficient charge recovery logic circuit", IEEE Solid-State Circuits, vol. 31, no. 4, pp.514-522, Apr. 1996.
- Y. Ye and K. Roy, “quasi-static energy recovery logic,” Solid-State Circuits, IEEE Journal of, vol. 36, no. 2, pp. 239–248, Feb. 2001.
- Y. Takahashi, K. Konta, K. Takahashi, M. Yokoyama, K. Shouno, and M. Mizunuma, “Carry propagation free adder/subtracted using adiabatic dynamic cmos logic circuit technology,” Fundamentals of Electronics, Communications and Computer Sciences, IEICE Transactions on, vol.E86-A, no.6,pp. 1437–1444, Jun 2003.
- V. De and J. Meindl, “Complementary adiabatic and fully adiabatic mos logic families for giga scale integration,” Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC, 1996 IEEE International, pp. 298–299, 461, Feb. 1996.
- Y. Takahashi, T. Sekine, and M. Yokoyama, “VLSI implementation of a 4x4-bit multiplier in a two phase drive adiabatic dynamic CMOS logic,” Electronics, IEICE Transactions on, vol. E90-C, no. 10, pp. 2002– 2006, Oct 2007.