Open Access Journal

ISSN : 2394-2320 (Online)

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

Open Access Journal

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

ISSN : 2394-2320 (Online)

Call For Paper : Vol 11, Issue 03, March 2024

Call for Paper

Vol 11, Issue 03, March 2024

Indexing

Implementation of Logic Circuits with Low Energy Charge Recovery Logic

Author : Deepak Mittal 1 Anjan Kumar 2

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Date of Publication :22nd February 2018

Abstract: Various energy recovery circuits have been proposed for reducing the power dissipation in CMOS logic circuits. This paper presents three Logic Circuits implemented using charge recovery logic. They are completely unique boost logic known as pseudo-NMOS boost logic (PNBL), to get low energy consumption and efficient-speed as compare to CMOS binary logic. PNBL is faster and compact charge recovery logic and it related to boost logic family. These logic circuits have less operating energy dissipation due to charge recovery logic. To exhibit the performance of Logic circuits are implemented with PNBL and compared with CMOS in 180nm technology. Simulation results show that logic circuits with PNBL recover the charge 57.14nJ at the frequency of 1GHZ that is approximately 105 times conserve energy as compared to conventional CMOS technology. Charge recovery logic also has one more advantage that it provided complemented and non-complemented both output at a time with small area trade-off.

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