Author : R.B.Aswathy 1
Date of Publication :29th March 2018
Abstract: Filter Bank Multicarrier (FBMC) systems are a subclass of multicarrier (MC) systems. While its basic principle is dividing frequency spectrum into many narrow sub-channels. Filter Bank multicarrier aims to overcome the shortcomings that were encountered with the OFDM, Orthogonal Frequency Division Multiplexing. Field- Programmable Gate Arrays (FPGA’s) are especially suited to fulfill these requirements. FPGA’s are very powerful, relatively inexpensive, and adaptable since their configuration is specified in an abstract hardware description language. The aim of this work is to design a receiver side of FBMC in FFT and pipelined FFT structure with improved throughput, BER, and bandwidth range using Verilog HDL and implement it on FPGA. Here the results are obtained using MATLAB and Verilog HDL implemented on Spartan-6 FPGA board. The result of FFT and the pipeline FFT with timing summary is computed and the performance of FBMC is improved by adding the FIR filter at the receiver side. Filters usually low pass filters are uniformly spaced and are higher in selectivity to achieve minimum crosstalk
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