Open Access Journal

ISSN : 2394-2320 (Online)

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

Open Access Journal

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

ISSN : 2394-2320 (Online)

Call For Paper : Vol 11, Issue 03, March 2024

Call for Paper

Vol 11, Issue 03, March 2024

Indexing

A Novel Low-Power Reversible Vedic Multiplier

Author : P.Kiran Kumar 1 E.Padmaja 2

PDF

Date of Publication :22nd February 2018

Abstract: In reversible computing, modelling low-power circuits is one of the most important technique. As a result of its wide range of applications, major works have been proposed in realizing reversible circuits including primary reversible gates and adders. In reversible computation, multiplier circuits play a vital role in practical applications like quantum dot cellular automata, DNA computing, nanotechnology and low-power CMOS designs. Hence superior multiplier architectures are bound to increase the efficiency of the system. The Vedic multiplier is one such optimistic solution. Implementing this with reversible logic further decreases power dissipation. In this paper, a novel reversible Vedic multiplier is proposed by making use of an algorithm or sutra called Urdhva Tiryagbhyam meaning vertical & crosswise. The power dissipation of proposed reversible multiplier design is reduced by 72.47 %. The reduction in power dissipation is highly achieved by reducing the number of gates which comprise reduction of 12.5 %. The constant inputs are reduced by 16.5 % and a reduction of 28 % is obtained in garbage outputs.

Reference :

    1. R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of Research and Development, vol. 5, no. 3, pp. 183–191, July 1961.
    2. C. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, vol. 17, no. 6, pp. 525–532, Nov 1973.
    3. M. C. Parker and S. D. Walker, “Is computation reversible?” Optics communications, vol. 271, no. 1, pp. 274–277, 2007.
    4. T. Chattopadhyay, “Optical logic circuits using double controlled logic gate,” Optoelectronics, IET, vol. 7, no. 5, pp. 99–109, October 2013.
    5. S. Burignat, M. K. Thomsen, M. Klimczak, M. Olczak, and A. De Vos, “Interfacing reversible pass-transistor cmos chips with conventional restoring cmos circuits,” in Reversible Computation. Springer, 2012, pp. 112–122.
    6. P. Gupta, A. Agrawal, and N. Jha, “An algorithm for synthesis of reversible logic circuits,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, no. 11, pp. 2317–2330, Nov 2006.
    7. R. Feynman, “Quantum mechanical computers,” Foundations of Physics, vol. 16, no. 6, pp. 507–531, 1986.
    8. T. Toffoli, “Reversible computing,” in Automata, Languages and Pro-gramming, ser. Lecture Notes in Computer Science, J. de Bakker and J. van Leeuwen, Eds. Springer Berlin Heidelberg, 1980, vol. 85, pp. 632–644.
    9. E. Fredkin and T. Toffoli, “Conservative logic,” International Journal of Theoretical Physics, vol. 21, no. 3- 4, pp. 219–253, 1982.
    10. A. Sarker, A. N. Bahar, P. K. Biswas, and M. Morshed, “A novel presentation of peres gate (pg) in quantum-dot cellular automata (qca),” European Scientific Journal, vol. 10, no. 21, 2014.
    11. S. Mahammad and K. Veezhinathan, “Constructing online testable circuits using reversible logic,” Instrumentation and Measurement, IEEE Transactions on, vol. 59, no. 1, pp. 101–109, Jan 2010.
    12. M. Morrison and N. Ranganathan, “Synthesis of dualrail adiabatic logic for low power security applications,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 33, no. 7, pp. 975– 988, July 2014.
    13. Jagadguru Swami Sri Bharathi Krishna Tirthji Maharaja, “Vedic math-ematics,” 1986.
    14. M. Haghparast, S. Jassabi, K. Navi, and O. Hashemipour, “Design of a novel reversible multiplier circuit using hng gate in nanotechnology,” in World Applied Science Journal, 2008. IEEE, 2008, pp. 974–978.
    15. H. Bhagyalakshmi and O. Venkatesha, MK, “An improved design of a multiplier using reversible logic gates,” in International Journal of Engineering Science and Technology, 2010. IJEST, 2010, pp. 3838– 3845.
    16. F. Naderpour and A. Vafaei, “Reversible multipliers: decreasing the depth of the circuit,” in Electrical and Computer Engineering, 2008. ICECE 2008. International Conference on. IEEE, 2008, pp. 306–310.
    17.  A. Banerjee and A. Pathak, “An analysis of reversible multiplier cir-cuits,” arXiv preprint arXiv:0907.3357, 2009.
    18. A. Hatkar, A. Hatkar, and N. Narkhede, “Asic design of reversible mul-tiplier circuit,” in Electronic Systems, Signal Processing and Computing Technologies (ICESC), 2014 International Conference on. IEEE, 2014, pp. 47–52.
    19. Y. Van Rentergem and A. De Vos, “Optimal design of a reversible full adder,” International Journal of Unconventional Computing, vol. 1, no. 4, p. 339, 2005.

Recent Article