Open Access Journal

ISSN : 2394-2320 (Online)

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

Open Access Journal

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

ISSN : 2394-2320 (Online)

Reference :

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    2. S.Karthik and Priyanka Udayabhanu, “FPGA Implementation of High Speed Vedic Multipliers”, International Journal of Engineering Research & Technology, Volume I, Issue-10, December 2012.
    3.  IsraekKoren, “Computer Arithmetic Algorithms”, 2nd ed., Universities Press, 2003.
    4. Mohamed Raffiquzzaman, Chandra Rajan, “Modern Computer Architecture”, 1st ed., Galgotia Publication pvt.Ltd., 2008.
    5. U.G. Nawathe, M. Hassan, K.C. Yen, and A. Kumar, “Implementation of an 8-Core, 64-Thread, PowerEfficient SPARC Server on a Chip”, IEEE Journal of SolidState Circuits, vol. 43, no. 1, pp. 6-20, January, 2008.
    6. Varsharani V H, Prabha S K, B.P. Patil, “Performance Evaluation of Proposed Vedic Multiplier inMicrowind”, International Journal of Communication Engineering Applications, Vol. 3, Issue. 3, pp. 498-502, July 2012.
    7. R. K. Bathija, R. S. Meena, S. Sarkar, Rajesh Sahu, “Low Power High Speed 16x16 Multiplier Using Vedic Mathematics”, International Journal of Computer Applications, Vol. 59, No. 6, pp. 41-44, December, 2012.
    8. Premananda B. S, Samarth S. Pai, Shashank B, Shashank S. Bhat, “Design and Implementation of 8-bit Vedic Multiplier”, International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, Vol. 2, Issue 12, pp. 5877-5882, December, 2013.
    9. Sowmiya M, Nirmal Kumar R, S Valamathy, Karthick, “Design of Efficient Vedic Multiplier By The Analysis Of Adders”, International Journal of Emerging Technology and Advanced Engineering, Vol. 3, Issue 1, pp. 396-403, January, 2013.
    10. Ramesh Pushpangadan, VineethSukumaran, Rino Innocent, Dinesh Sasikumar, VaisakSundar, “High Speed Vedic Multiplier for Digital Signal Processors”, IETE Journal of Research, Vol. 55, Issue 6, pp. 282-286, November-December, 2009.
    11. P. Mehta, D. Gawali, Conventional versus Vedic mathematical method for hardware implementation of a multiplier, in: Proceedings of the IEEE International Conference on Advances in Computing, Control, and Telecommunication, Trivandrum, Kerala, December 2009, pp. 640–642
    12. SreeehariVeeramachaneni M.B. Srinivas, “Novel High-Speed Architechture for 32-Bit Binary Coded Decimal (BCD) Multiplier”, International Symposium on Communication and Information Technologies (ISCIT), 21 - 23 October, 2008.
    13.  J. Rabaey, A. Chandrakasan, and B. Nikolic, “Digital Integrated Circuits”, 2nd ed., Prentice Hall Pears.

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