1. 1. Jaume Segura, Charles F. Hawkins CMOS electronics: how it works, how it fails, Wiley-IEEE, 2004, page 132
   2. Clive Maxfield Bebop to the Boolean boogie: an unconventional guide to electronics Newnes, 2008, pp. 423- 426
   3. Albert Raj/Latha VLSI Design PHI Learning Pvt. Ltd. pp. 150-153
   4. Yano, K, et al, "A 3.8 ns CMOS 16*16b multiplier using complementary pass transistor logic", IEEE J. Solid State Circuits, Vol 25, p388-395, April 1990
   5. Yingtao Jiang, Abdulkarim Al-Sheraidah, Yuke Wang, Edwin Sha, and Jin-Gyun Chung, “A Novel MultiplexerBased Low-Power Full Adder” IEEE Transaction on circuits and systems-II: Express Brief, Vol. 51, No. 7,p345, July- 2004
   6. Makoto Suzuki, et al, "A 1.5 ns 32 b CMOS ALU in double pass transistor logic", ISSCC Dig. Tech. Papers, pp 90-91, February 1993.
   7. N. Ohkubo, et al, "A 4.4 ns CMOS 54X54 b multiplier using pass transistor multiplexer", Proceedings of the IEEE 1994 Custom Integrated Circuit Conference, May 1-4 1994, p599-602, San Diego, California.
   8. Mohamed W.Allam, “New Methodologies for LowPower High Performance Digital VLSI Design”, PhD. Thesis, University of Waterloo, Ontario, Canada, 2000
   9. A.Bazzazi and B.Eskafi, "Design and Implementation of Full Adder Cell with the GDI Technique Based on 0.18μm CMOS Technology", International Multi Conference of Engineers and Computer Scientists (IMES) Vol II, March 17 - 19, 2010, Hong Kong
   10. Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner, "Gate Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits", IEEE Transaction on VLSI Systems, Vol. 10
   11. Dan Wang. "Novel low power full adder cells in 180nm CMOS technology", 2009 4th IEEE Conference on Industrial Electronics and Applications, 05/2009
   12. L.Bisdounis, D.Gouvetas and O.Koufopavlou, “A comparative study of CMOS circuit design styles for lowpower high-speed VLSI circuits” Int. J. of Electronics, Vol.84, No.6, pp 599-613,1998. Anu Gupta, Design Explorations of VLSI Arithmetic Circuits, Ph.D. Thesis, BITS,Pilani, India, 2003.
   13. R.Uma and P. Dhavachelvan,” Modified Gate Diffusion Input Technique: A New Technique for Enhancing Performance in Full Adder Circuits” 2nd International Conference on Communication, Computing & Security [ICCCS-2012].
   14. R.uma, Vidya Vijayan, M. Mohanapriya, Sharon Paul, Area, Delay and Power Comparison of Adder Topologies
   15. M. Aguirre and M. Linares, “An alternative logic approach to implement high-speed low-power full adder cells,” in Proc. SBCCI, Florianopolis,Brazil, Sep. 2005, pp. 166–171.
   16. A. M. Shams and M. Bayoumi, “Performance evaluation of 1-bit CMOS adder cells,” in Proc. IEEE ISCAS, Orlando, FL, May 1999,vol. 1, pp. 27–30.
   17. I. S. Abu-Khater, A. Bellaouar, and M. I. Elmastry, “Circuit techniques for CMOS low-power highperformance multipliers,” IEEE J. Solid-State Circuits, vol. 31, pp. 1535–1546, Oct. 1996.